1. Field of the Disclosure
The present disclosure relates to a liquid crystal display (LCD) device, and more particularly, to an LCD device in which a guide pattern for a seal pattern is formed to reduce a design margin during formation of the seal pattern so that a narrow bezel can be embodied.
2. Discussion of the Related Art
In recent years, with the advent of information-oriented society, display devices configured to process and display a large amount of information have been developed at a high speed. Among the display devices, LCD devices have lately been developed as highly efficient flat panel display (FPD) devices, which may be made ultrathin and lightweight and consume low power to supersede conventional cathode ray tubes (CRTs).
Among the LCD devices, an active-matrix-type LCD including an array substrate in which a thin film transistor (TFT) serving as a switching device capable of controlling on/off states of a voltage in each of pixels is provided has attracted much attention because the active-matrix-type LCD has a high resolution and is highly capable of embodying moving images.
FIG. 1 is a schematic plan view of a conventional liquid crystal display (LCD) device, and FIG. 2 is a schematic cross-sectional view of portion A of FIG. 1.
As shown in FIG. 1, the LCD device may include a first substrate 10 on which a thin film transistor (TFT) Tr serving as a switching device and a pixel electrode 50 are formed, a second substrate 60 on which a common electrode 66 is formed, an LC layer 70 interposed between the first and second substrates 10 and 60, and a seal pattern 80 configured to bond the first and second substrates 10 and 60 to each other to prevent leakage of LCs from the LC layer 70. The first and second substrates 10 and 60 may be disposed opposite each other.
A display region DR and a non-display region NDR may be defined on the first substrate 10. The display region DR may be configured to display images, and the non-display region NDR may be disposed adjacent to the display region DR. The seal pattern 80 may be disposed in the non-display region NDR.
Gate lines (not shown) and data lines (not shown) may be formed on the first substrate 10 to enable switching operations of the TFT Tr. A driver configured to apply signals to the gate lines and the data lines may be formed on at least one side of the first substrate 10. In this case, to connect the driver with an external driver circuit, the second substrate 60 may have a smaller size than the first substrate 10 and expose at least one side of the first substrate 10.
The TFT Tr may include a gate electrode 14 connected to the gate line, a gate insulating layer 20 covering the gate electrode 14, a semiconductor layer 22 disposed on the gate insulating layer 20 and including an active layer 22a formed of pure amorphous silicon (a-Si) and an ohmic contact layer 22b formed of doped a-Si, a source electrode 32 disposed on the semiconductor layer 22 and connected to the data line, and a drain electrode 34 disposed on the semiconductor layer 22 and spaced apart from the source electrode 32.
A protection layer 40 having a drain contact hole 42 exposing the drain electrode 34 may be formed to cover the TFT Tr. A pixel electrode 50 may be formed on the protection layer 40 and connected to the drain electrode 34 through the drain contact hole 42. The pixel electrode 50 may be disposed in each of pixel regions P defined by intersections between the gate lines and the data lines.
In addition, a black matrix 62, a color filter layer 64, and a common electrode 66 may be formed on the second substrate 60 disposed opposite the first substrate 10. The black matrix 62 may cover the gate line and the data line, the color filter layer 64 may correspond to the pixel region P, and the common electrode 66 may be configured to form an electric field along with the pixel electrode 50.
The LC layer 70 may be disposed between the first and second substrates 10 and 60, that is, between the pixel electrode 50 and the common electrode 66, and LC molecules of the LC layer 70 may be driven due to an electric field formed between the pixel electrode 50 and the common electrode 66.
As described above, the seal pattern 80 may be formed in the non-display region NDR to prevent leakage of LCs from the LC layer 70 and bond the first and second substrates 10 and 60 to each other. One end of the seal pattern 80 may be in contact with the protection layer 40, and the other end thereof may be in contact with the second substrate 60.
The seal pattern 80 may be formed by coating a sealant on the first substrate 10 or the second substrate 60 using a dispenser.
However, the seal pattern 80 may depart from a desired position during the formation thereof.
A deviation in the position of the seal pattern 80 will be described in further detail with reference to FIGS. 3A and 3B.
Initially, as shown in FIG. 3A, when the sealant is coated with a dispenser (not shown) located in a first position PO1, the seal pattern 80 may be formed in a desired position. However, as shown in FIGS. 3B and 3C, when the sealant is coated with the dispenser deviated from the first position PO1 and located in a second position PO2 or third position PO3, a deviation DV caused by the spread of the sealant may occur during a bonding process, so the sealant 80 may depart from a desired position.
A region in which the sealant 80 is to be formed should increase by as much as the deviation DV in consideration of the deviation DV, so that the non-display region NDR may increase. That is, embodying a narrow bezel required by an LCD may be hindered.